1. Field of the Invention
The invention relates to metal-insulator-metal capacitors, and more particularly to a metal-insulator-metal capacitor structure and method of manufacturing a high density of metal-insulator-metal capacitors in a VLSI circuit.
2. Background Description
Metal-insulator-metal capacitors (MIMCAP) are important components in memory, logic and analog circuits. MIMCAPs are typically fabricated with metal interconnections and do not utilize valuable silicon real estate. In contrast, a conventional silicon based diffusion capacitor suffers from poor efficiency as internal serial resistance increases, adding an unwanted resistance-capacitance intrinsic delay to the capacitor.
Horizontal Plate MIMCAP structures having a planar design have been introduced into integrated circuits in the back-end-of-line (BEOL) manufacturing steps. Such BEOL designs require dielectric materials with low processing temperatures to avoid damaging previously fabricated structures on the silicon chip. These dielectric materials typically include silicon oxide (SiO2) or silicon nitride (Si3N4) deposited using plasma enhanced chemical vapor deposition (PECVD) with capacitance densities on the order of 1–1.5 fF/um2. Thus, horizontal plate capacitor structures demand large silicon chip area to form capacitors of needed capacitance.
The continual shrinking of VLSI circuits requires reducing the planar area allocated to horizontal plate MIMCAPS on the silicon chip while the capacitance requirements are maintained. One way of reducing planar area requirements while maintaining the necessary capacitance includes decreasing insulator thickness between the capacitor plates. However, insulator thickness scaling of the current materials has reached a design road block because of the exponential increase in leakage currents, increase in the voltage linearity, and reduction in lifetime reliability which are a consequence of thinner insulating films. For example, FIGS. 1 and 2 show the increase in leakage currents and voltage/capacitance non-linearity, respectively, as a function of insulator thinning. FIG. 1 shows leakage current increasing along the y-axis as bias voltage increases along the x-axis. The relationship becomes increasingly non-linear at thinner insulating film thicknesses. FIG. 2 shows an increasingly non-linear relationship between capacitance on the y-axis and voltage on the x-axis for thinner insulators. At reduced thicknesses, the capacitance/voltage relationship becomes sufficiently non-linear as to require more complicated circuit designs.
One method to conserve surface area is to build capacitors in the vertical dimension. Some vertical designs take advantage of a deep trench structure formed in the silicon chip including forming the MIMCAP on the sidewalls and the bottoms of the trench. Such trenches are formed in the BEOL due to the constraints of low-temperature metal processing. In other words, the MIMCAP must be formed towards the end of the fabrication process to avoid damage to the MIMCAP structure during subsequent processing steps. Other designs avoid MIMCAP damage during fabrication by forming deep trenches in the silicon substrate and using a metal with a high melting temperature such as tungsten, or doped polysilicon to form electrodes. Such high-melting temperature metals will successfully survive any subsequent processing steps.
However, deep trench structure MIMCAPs result in high processing costs. Therefore, other types of vertical MIMCAP designs have been proposed. For example, one MIMCAP design of reduced costs includes etching insulating material in the BEOL to form a shallow-trench structure so that surface area available for capacitor plate formation is increased without increasing real estate usage on the silicon chip surface. By forming the capacitor plates along the surfaces of the shallow-trenches, a structure having a so called semi-interdigitated MIMCAP may be formed. The semi-interdigitated design increases the surface area of the global charge capacitive plates significantly with little increase in chip surface area usage.
It is also known that some MIMCAP designs, especially those of a vertical MIMCAP structure, require many extra processing steps that are typically not easily integratable into a conventional BEOL process. For example, the semi-interdigitated MIMCAP design described above does not allow all the nodes of the capacitive plates to couple to one another at all surfaces. In other words, the surface efficiency or utilized surface area of the capacitive plates is only 50 to 60%. This reduction in utilized area has driven research and development into alternative high dielectric constant (high-k) materials for MIMCAP insulating films such as Al2O3, Ta2O5 HfO2 and laminate stacks thereof. Such high-k materials allow for high capacitance values for a given insulator film thickness.
But the introduction of high-k materials requires integrating processing steps into the fabrication process such as reactive ion etching (RIE) to pattern the MIMCAP area. The RIE patterning of these materials is expensive and in some cases requires plasma etching at elevated temperatures and/or a dual step process of plasma or implant damage followed by a wet chemical etch. This subsequently drives up the manufacturing cost of the MIMCAP capacitor. Hafnium oxide (HfO2) is an example of a high-k insulating film candidate which is difficult to etch and thus expensive to incorporate into MIMCAP design.
The invention is designed to solve one or more of the above problems.